If this element is present, the existance of the port is controlled by the specified value. valid values are 'illegal', 'required' and 'optional'. Group of elements used in a transactional port. If this element is present, the type of access is restricted to the specified value. If this element is present, the width must match If this element is present, the name must match Group of elements used in a wire port. Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1. false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped. If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface. Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a 'mode' bus interface or a mirrored-'mode' bus interface. Otherwise they only apply when the port appears in a 'mode' bus interface. Specifies default constraints for the enclosing wire type port when it appears in a mirrored-'mode' bus interface. Define the ports and other information of a particular abstraction of the bus Reference to the busDefinition that this abstractionDefinition implements. Optional name of abstraction type that this abstraction definition is compatible with. This abstraction definition may change the definitions of ports in the existing abstraction definition and add new ports, the ports in the original abstraction are not deleted but may be marked illegal to disallow their use. This abstraction definition may only extend another abstraction definition if the bus type of this abstraction definition extends the bus type of the extended abstraction definition This is a list of logical ports defined by the bus. The assigned name of this port in bus specifications. If this element is enabled (true) it is an error if the port is not mapped on both sides of the connection. A port that carries complex information modeled at a high level of abstraction. The type of information this port carries A transactional port can carry both address and data information. Defines constraints for this port when present in a system bus interface with a matching group name. Used to group system ports into different groups within a common bus. Defines constraints for this port when present in a initiator bus interface. Defines constraints for this port when present in a target bus interface. A port that carries logic or an array of logic values The type of information this port carries A wire port can carry both address and data, but may not mix this with a clock or reset Defines constraints for this port when present in a system bus interface with a matching group name. Used to group system ports into different groups within a common bus. Defines constraints for this port when present in a initiator bus interface. Defines constraints for this port when present in a target bus interface. Indicates the default value for this wire port.