'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. The number of bits in the least addressable unit. The default is byte addressable (8 bits). Describes one of the bus interfaces supported by this component. A list of bus interfaces supported by this component. Type definition for a busInterface in a component The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes along with any configurable element values needed to configure this interface. Indicates the usage mode of this instance of the bus interface. Indicates whether a connection to this interface is required for proper component functionality. Indicates whether bit steering should be used to map this interface onto a bus of different data width. Values are "0", "1" (defaults to "0"). 'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. Indicates which system interface is being mirrored. Name must match a group name present on one or more ports in the corresonding bus definition. Lists all channel connections between mirror interfaces of this component. Defines a set of mirrored interfaces of this component that are connected to one another. Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment. Group of the different modes a busInterface can take on in a component If this element is present, the bus interface can serve as a initiator. This element encapsulates additional information related to its role as initiator. If this initiator connects to an addressable bus, this element references the address space it maps to. If the initiator's mapping to the physical address space is not zero based, the baseAddress element may be used to indicate the offset. If not specified the offset is 0. The baseAddress is in units of the addressSpace addressUnitBits Base of an address space. A reference to a mode. If this element is present, the bus interface can serve as a target. This reference is used to point the filesets that are associated with this target port. Depending on the target port function, there may be completely different software drivers associated with the different ports. Abritray name assigned to the collections of fileSets. If this element is present, the bus interface is a system interface, neither initiator nor target, with a specific function on the bus. If this element is present, the bus interface represents a mirrored target interface. All directional constraints on ports are reversed relative to the specification in the bus definition. Represents a set of remap base addresses. Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The modeRef element indicates the name of the mode for which this address is valid. The address range of mirrored target, expressed as the number of bitsInLAU from the containing busInterface. If this element is present, the bus interface represents a mirrored initiator interface. All directional constraints on ports are reversed relative to the specification in the bus definition. If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition. Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The ipxact:group element must be specified if monitoring a system interface. Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition. If this element is present, it indicates that the bus interface provides a transparent bridge to another initiator bus interface on the same component. It has a initiatorRef attribute which contains the name of the other bus interface. Any target interface can bridge to multiple initiator interfaces, and multiple target interfaces can bridge to the same initiator interface. The name of the initiator bus interface to which this interface bridges. Group of the different modes a busInterface can take on in an abstractor If this element is present, the bus interface can serve as a initiator. This element encapsulates additional information related to its role as initiator. If this element is present, the bus interface can serve as a target. If this element is present, the bus interface is a system interface, neither initiator nor target, with a specific function on the bus. If this element is present, the bus interface represents a mirrored target interface. All directional constraints on ports are reversed relative to the specification in the bus definition. If this element is present, the bus interface represents a mirrored initiator interface. All directional constraints on ports are reversed relative to the specification in the bus definition. If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition. Type definition for a busInterface in a component Describes one of the bus interfaces supported by this component. A list of bus interfaces supported by this component. Type definition for a indirectInterface in a component A reference to a memoryMap. This memoryMap is indirectly accessible through this interface. 'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. A reference to a field used for addressing the indirectly accessible memoryMap. A reference to a field used for read/write access to the indirectly accessible memoryMap. The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes along with any configurable element values needed to configure this abstraction. Bus definition can be found through a reference in this file. A reference to a view name in the file for which this type applies. Provides the VLNV of the abstraction type. Listing of maps between component ports and bus ports. Maps a component's port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component. Logical port from abstraction definition Bus port name as specified inside the abstraction definition Physical port from this component Component port name as specified inside the model port section Component port subPort name as specified inside the model port section Identifies a value to tie this logical port to. When true, indicates that this portMap element is for information purpose only. Indicates that the connection between the logical and physical ports should include an inversion.