Indicates legal cell function values. Indicates legal cell class values. Indicates legal cell strength values. Indicates legal values for edge specification attributes. Indicates the type of delay value - minimum or maximum delay. Type used to record percentage values. List of clocks associated with the component that are not associated with ports. Set the clockSource attribute on the clockDriver to indicate the source of a clock not associated with a particular component port. Used to provide a generic description of a technology library cell. Defines a technology library cell in library independent fashion, based on specification of a cell function and strength. Defines a technology library cell in library independent fashion, based on specification of a cell class and strength. Indicates the desired strength of the specified cell. Defines a timing constraint for the associated port. The constraint is relative to the clock specified by the clockName attribute. The clockEdge indicates which clock edge the constraint is associated with (default is rising edge). The delayType attribute can be specified to further refine the constraint. Indicates the clock edge that a timing constraint is relative to. Indicates the type of delay in a timing constraint - minimum or maximum. Indicates the name of the clock to which this constraint applies. Defines a constraint indicating how an input is to be driven. The preferred methodology is to specify a library cell in technology independent fashion. The implemention tool should assume that the associated port is driven by the specified cell, or that the drive strength of the input port is indicated by the specified resistance value. Defines a constraint indicating the type of load on an output port. Indicates how many loads of the specified cell are connected. If not present, 3 is assumed. Defines constraints that apply to a component port. If multiple constraintSet elements are used, each must have a unique value for the constraintSetId attribute. The optional element vector specify the bits of a vector for which the constraints apply. The vaules of left and right must be within the range of the port. If the vector is not specified then the constraints apply to all the bits of the port. The optional elements left and right can be used to select a bit-slice of a vector. The optional elements left and right can be used to select a bit-slice of a vector. Indicates a name for this set of constraints. Constraints are tied to a view using this name in the constraintSetRef element. List of constraintSet elements for a component port. A reference to a set of port constraints. Defines constraints that apply to a wire type port in an abstraction definition.