Design instantiation type. References an IP-XACT design document (by VLNV) that provides a design for the component. Design configuration instantiation type. The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. References an IP-XACT design configuration document (by VLNV) that provides a configuration for the component's design. Component instantiation type When true, indicates that this component should not be netlisted. The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. A string specifying the library name in which the model should be compiled. If the libraryName element is not present then its value defaults to “work”. A string describing the VHDL package containing the interface of the model. If the packageName element is not present then its value defaults to the component VLNV name concatenated with postfix “_cmp_pkg” which stands for component package. A string describing the Verilog, SystemVerilog, or SystemC module name or the VHDL entity name. If the moduleName is not present then its value defaults to the component VLNV name A string describing the VHDL architecture name. If the architectureName element is not present then its value defaults to “rtl”. A string describing the Verilog, SystemVerilog, or VHDL configuration name. If the configurationName element is not present then its value defaults to the design configuration VLNV name of the design configuration associated with the active hierarchical view or, if there is no active hierarchical view, to the component VLNV name concatenated with postfix “_rtl_cfg”. Model parameter name value pairs container A module parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used. Default command and flags used to build derived files from the sourceName files in the referenced file sets. Container for clear box element references. Reference to a clear box element which is visible within this view. Component Instantiation Design Instantiation Design Configuration Instantiation Model information. Views container Single view of a component Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. Instantiations container Component, design, designConfiguration instantiation view of a component Port container Model information for an abstractor. Views container Single view of an abstracto Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. Instantiations container Component Instantiation Port container Model information. Reference to a clearboxElement within a view. The 'name' attribute must refer to a clearboxElement defined within this component. The contents of each location element can be used to specified one location (HDL Path) through the referenced clearBoxElement is accessible. Reference to a clearboxElement defined within this component. A value of 'true' indicates that this value must match the language being generated for the design.