The direction of a component port. A port description, giving a name and an access type for high level ports. Port style Defines a port whose type resolves to simple bits. Defines a port that implements or uses a service that can be implemented with functions or methods. Represents a port that has subport structure. Port access characteristics. A port description, giving a name and an access type for high level ports. Port style Defines a port whose type resolves to simple bits. Defines a port that implements or uses a service that can be implemented with functions or methods. Represents a port that has subport structure. Port access characteristics. If this element is present, the type of access is restricted to the specified value. defines the bus size in bits. This can be the result of an expression. defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed by pointer. defines the structure of data transported by this port Defines the name of the payload. For example: TLM2 or TLM1 Defines the type of the payload. Defines the name of the payload extension. If attribute is not specified, it is by default optional. True if the payload extension is mandatory. list of port type parameters (e.g. template or constructor parameters for a systemC port or socket) A typed parameter name value pair. The optional attribute dataType defines the type of the value and the usageType attribute indicates how the parameter is to be used. Definition of a single transactional type defintion The name of the port type. Can be any predefined type such sc_port or sc_export in SystemC or any user-defined type such as tlm_port. When false, defines that the type is an abstract type that may not be related to an existing type in the language of the referenced view. Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition. A reference to a view name in the file for which this type applies. Definition of a single service type defintion The name of the service type. Can be any predefined type such as booean or integer or any user-defined type such as addr_type or data_type. Defines that the typeName supplied for this service is implicit and a netlister should not declare this service in a language specific top-level netlist Where the definition of the type is contained if the type if not part of the language. For SystemC and SystemVerilog it is the include file containing the type definition. Definition of a single wire type defintion that can relate to multiple views. The name of the logic type. Examples could be std_logic, std_ulogic, std_logic_vector, sc_logic, ... Defines the types for the port has constrained the number of bits in the vector Where the definition of the type is contained. For std_logic, this is contained in IEEE.std_logic_1164.all. For sc_logic, this is contained in systemc.h. For VHDL this is the library and package as defined by the "used" statement. For SystemC and SystemVerilog it is the include file required. For verilog this is not needed. A reference to a view name in the file for which this type applies. The group of wire type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types. The group of transactional type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types. Describes port characteristics. Maps slices of this port to component field slices. Reference to a register field slice A reference to a mode. Listing of maps between component port slices and field slices. Wire port type for a component. The direction of a wire style port. The basic directions for a port are 'in' for input ports, 'out' for output port and 'inout' for bidirectional and tristate ports. A value of 'phantom' is also allowed and define a port that exist on the IP-XACT component but not on the HDL model. The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset. Vectored information. Wire port power constraints. Single wire port set of power constraints. True if logical ports with different directions from the physical port direction may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all direction value to be mapped onto the physical port. Also ignored for inout ports, since any logical port maybe mapped to a physical inout port. Transactional port type. Defines how the port accesses this service. Define the kind of transactional port Defines the bus width in bits.This can be the result of an expression. The type of information this port carries A transactional port can carry both address and data information. Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV). Bounds number of legal connections. Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections. Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1. Wire port power constraints. Single wire port set of power constraints. True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for "both" ports, since any logical port may be mapped to a physical "both" port. Transactional port type. Defines how the port accesses this service. Define the kind of transactional port Defines the bus width in bits.This can be the result of an expression. The type of information this port carries A transactional port can carry both address and data information. Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV). Bounds number of legal connections. Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections. Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1. True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for "both" ports, since any logical port may be mapped to a physical "both" port. Wire port type for an abstractor. The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset. Vectored information. Left and right ranges of the vector. Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed through a pointer. Definition of a single signal type defintion that can relate to multiple views. defines the signal type for the port. Continuous-conservative is a signal which is continuous in time and quantity, where the quantity represents voltage and current to capture the conservative behavior of an electrical network (i. e. Kirchhoff’s Laws apply), and which has no direction. Continuous-non-conservative is a directed signal which is continuous in time and quantity, where the quantity represents either a voltage or a current (often called signal flow). In this case it only captures the non-conservative behavior of a set of interconnected components. Discrete is a directed sampled signal which is time-discrete and value-continuous (the value may also be quantified), where the value represents either a voltage or a current (other representations are possible also). It captures the non-conservative behavior of a set of interconnected components. Digital is a time-discrete and value-discrete signal. The interpretation of the signal values is described by the wireTypeDefs. A reference to a view in the file for which this type applies. Definition of a single domain type defintion that can relate to multiple views. The name of the domain. Where the definition of the type is contained. A reference to a view in the file for which this type applies. The group of domain type definitions. The group of signal type definitions. The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset. Specific left and right array bounds. Defines the types for the port has constrained the number of bits in the vector Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition. Indicates the role that this structured port plays in the connection. Only valid for structured ports with structType='interface'. In SystemVerilog, this indicates the modport for the SystemVerilog interface corresponding to this structuredPortType. A reference to a view name in the file for which this type applies. A port description, giving a name and an access type for high level ports. Port style Defines a port whose type resolves to simple bits. Port access characteristics. When present and set to 'true' identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType='interface'. A port description, giving a name and an access type for high level ports. Port style Defines a port whose type resolves to simple bits. Port access characteristics. When present and set to 'true' identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType='interface'. Determines the type of structured port. Can be one of "struct', 'union', or 'interface'. Vectored information. When not present or set to 'true' indicates that this structured port is 'packed'. If present and set to 'false', indicates that this structured port is 'unpacked'. Determines the type of structured port. Can be one of "struct', 'union', or 'interface'. Vectored information. When not present or set to 'true' indicates that this structured port is 'packed'. If present and set to 'false', indicates that this structured port is 'unpacked'. Power domain. It is the user’s responsibility to ensure it matches an existing power domain in UPF/CPF file. Boolean value. If set to true, then the domain/port is always powered, whatever its power domain. Only applies for output ports. The direction of a wire style port. The basic directions for a port are 'in' for input ports, 'out' for output port and 'inout' for bidirectional and tristate ports. A value of 'phantom' is also allowed and define a port that exist on the IP-XACT component but not on the HDL model. The direction of a wire style port. The basic directions for a port are 'in' for input ports, 'out' for output port and 'inout' for bidirectional and tristate ports. A value of 'phantom' is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.