Describes one of the bus interfaces supported by this component. A list of bus interfaces supported by this component. Uniquely names this bus interface. The bus type of this interface. Refers to a bus description using vendor, library and name attributes. If this element is present, the bus interface can serve as a master. This element encapsulates additional information related to its role as master. If this master connects to an addressable bus, this element references the address space it maps to. It has an addressSpaceRef attribute which is an addrSpaceID key ref. If master's mapping to the physical address space is not zero based, baseAddress and bitOffset elements may be used to indicate the offsets. If this element is present, the bus interface can serve as a slave. If this element is present, it indicates that the bus interface provides a bridge to another master bus interface on the same component. It has a masterRef attribute which contains the name of the other bus interface. It also has an opaque attribute to indicate that the bus bridge is opaque. Any slave interface can bridge to multiple master interfaces, and multiple slave interfaces can bridge to the same master interface. The name of the master bus interface to which this interface bridges. If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus. If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on signals are reversed relative to the specification in the bus definition. Represents a set of remap base addresses. Base of an address block. The state attribute indicates the name of the remap state for which this address is valid. The address range of mirrored slave. If this element is present, the bus interface represents a mirrored master interface. All directional constraints on signals are reversed relative to the specification in the bus definition. If this element is present, the bus interface represents a mirrored system interface. All directional constraints on signals are reversed relative to the specification in the bus definition. If this element is present, this interface represents an interface being exported from a sub-component. The type of interface (master, slave, ...) should be obtained from the sub-component interface. Indicates name of the sub-component containing the interface being exported. Indicates the name of the sub-component bus interface being exported. Directs how a bus interface is connected when the component is added to a design already containing a bus owner. Default behavior is "explicit". A bus instance is automatically chosen and the connection is made. Component addition fails if a suitable bus is not available. Connection of this bus interface is not made until the user explicitly requests connection. Maps component signals to bus signals. Maps a component's signal to a signal in a bus description. The text content of this element identifies a signal on this component bu its signal name. The busSignal attribute names the corresponding signal in the bus definition. The optional attributes left and right can be used to select a bit-slice of a signal vector to map to the bus interface. Master or slave index of this bus interface's connection on a bus. Only used on indexed buses. Indicates whether bit steering should be used to map this interface onto a bus of different data width. Values are "on", "off" or "default". Configuration generators for bus interfaces. Indicates which system interface is being mirrored. Name must match a group name present on one or more signals in the corresonding bus definition. Lists all channel connections between mirror interfaces of this component. Defines a set of mirrored interfaces of this component that are connected to one another. Overrides the maxMasters value in the bus definition if this number is more restrictive. Overrides the maxSlaves value in the bus definition if this number is more restrictive. Contains the name of one of the bus interfaces that is part of this channel. Contains a list of remap state names and associated signal values Contains a list of signals and values which tell the decoder to enter this remap state. The name attribute identifies the name of the state Contains the name and value of a signal on the component, the value indicates the logic value which this signal must take to effect the remapping. The id attribute stores the name of the signal which takes that value. This attribute identifies a signal on the component which affects the component's memory layout Stores the name of the state