The read/write accessability of an addess block. 'serial' or 'parallel' bank alignment. Describes the usage of an address block. Denotes an address range that can be used for read-write or read-only data storage. Denotes an address block that is used to communicate with hardware. Denotes an address range that must remain unoccupied. A reference to a unique address space. A reference to a unique memory map. Describes whether this bank's blocks are aligned in 'parallel' or 'serial'. For subspaceMap elements, this attribute identifies the master that contains the address space to be mapped. Base type for an element which references an address space. Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary. Base type for an element which references an memory map. Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary. Banks nested inside a bank do not specify address. Address blocks inside a bank do not specify address. Subspace references inside banks do not specify an address. Any parameters that may apply to the subspace reference. Field name. Offset of this field's lsb from bit 0 of the register. Width of the field in bits. Bit field description. Enumerates specific values that can be assigned to the bit field. Enumerated bit field value. Description of a bit field value. The name of this enumerated value. This may be used as a token in generating code. Maps in an address subspace from accross a bus bridge. Its masterRef attribute refers by name to the master bus interface on the other side of the bridge. It must match the masterRef attribute of a bridge element on the slave interface, and that bridge element must be designated as opaque. Map of address space blocks on slave slave bus interface. Memory map name, unique within the component. Put into a group to avoid making it a top level element Map of address space blocks on a slave bus interface in a specific remap state. State of the component in which the memory map is active. Map of address space blocks on the local memory map of a master bus interface. Address subspace type. Its subspaceReference attribute references the subspace from which the dimensions are taken. Any parameters that may apply to the subspace reference. Indicates whether the data is volatile, default to false when not present. Indicates the accessibility of the data in the address block. Possible values are 'read-write', 'read-only' and 'write-only'. This is a single contiguous block of memory inside a memory map. References the address space. The name of the address space is kept in its addressSpaceRef attribute. If this component is a bus master, this lists all the address spaces defined by the component. This defines a logical space, referenced by a bus master. The name of the address space. Unique within the model. Specifies the data storage as "big" or "little" endian. Provides the local memory map of an address space. Blocks in this memory map are accessable to master interfaces on this component that reference this address space. They are not accessable to any external master interface. Data specific to this address space. References the memory map. The name of the memory map is kept in its memoryMapRef attribute. Lists all the slave memory maps defined by the component. The set of address blocks a bus slave contributes to the bus' address space. Represents a bank of memory made up of address blocks or other banks. It has a bankAlignment attibute indicating whether its blocks are aligned in 'parallel' (occupying adjacent bit fields) or 'serial' (occupying contiguous addresses). Its child blocks do not contain addresses or bit offsets. Base of an address block. Base bit offset of an address block. If not included, it is assumed to be 0. The number of bits in the least addressable unit. The default is byte addressable (8 bits). This is a group of optional elements commonly added to various types of address blocks in a memory map. This group of elements describes an absolute or relative address of an address block in a memory map. Note that this is a group, not an element. It does not appear in the XML, but its contents may. This group of elements is common to top level banks and banked banks. An address block within the bank. No address information is supplied. A nested bank of blocks within a bank. No address information is supplied. This group of elements describes width and length of an address block in a memory map. Note that this is a group, not an element. It does not appear in the XML, but its contents may. The address range of an address block. Expressed as the number of addressable units accessable to the block. Bit width of an address block. If zero or absent and this is part of a slave memory map, the width is assumed to be the data width of the slave interface. It this is part of a local memory map, a missing width is assumed to be the effective width of the address space. If this is part of an address space definition, a missing width is assumed to be the widest data signal of all bus interfaces that reference this address space. This group of optional elements can be used to provide additional descriptions to an address block or bank. Note that this is a group, not an element. It does not appear in the XML, but its contents may. Indicates the usage of this block. Possible values are 'memory', 'register' and 'reserved'. Any additional parameters needed to describe this address block to the generators. This group of optional elements describes the memory mapped registers of an address block Register name. Dimensions a register array. Offset from baseAddress. Size in bits. Indicates that this register has a dependency on the setting of another register. The name of the register that enables this register. Name of the field within the register that enables this register. Value that the enabling field must be set to to enable this register. Mask to be anded with the value of the enabling field or register before comparing to the dependency value. Register value at reset. Describes individual bit fields within the register. Register description