Indicates legal units for capacitance values. Indicates legal units for resistance values. Indicates legal cell function values. Indicates legal cell class values. Indicates legal cell strength values. Indicates legal values for edge specification attributes. Indicates legal values for type of checking the paths apply to: setup or hold. Indicates legal values for associating a clock with timing exception. Indicates the type of delay value - minimum or maximum delay. Type used to record percentage values. Defines a non-negative floating point number. Indicates legal values for pathElement attribute Represents a simple capacitance value with optional units. Represents a simple delay value with optional units. Represents a simple resistance value with optional units. List of clocks associated with the component that are not associated with signals. Set the clockSource attribute on the clockDriver to indicate the source of a clock not associated with a particular component signal. Indicates the desired strength of the specified cell. Indicates the clock edge that a timing constraint is relative to. Indicates the path edge that a timing constraint is relative to. Indicates the type of path (setup/hold) that a timing constraint applies to. Indicates which clock (start/end) that a multi-cycle path is associated with. Indicates the type of delay in a timing constraint - minimum or maximum. Indicates the type of object that the pathSpecifier sub-element refers to. Indicates a name for this set of constraints. Constraints are tied to a view using this name in the constraintSetRef element. Used to indicate a particular technology library cell. Use of cellName is discouraged since it is technology dependent. Defines a technology library cell in library independent fashion, based on specification of a cell function and strength. Defines a technology library cell in library independent fashion, based on specification of a cell class and strength. Defines a technology library cell by name. Use of this library dependent syntax is discouraged as it is not portable. Defines a timing constraint for the associated signal. The constraint is relative to the clock specified by the clockName attribute. The clockEdge indicates which clock edge the constraint is associated with (default is rising edge). The delayType attribute can be specified to further refine the constraint. Defines a delay constraint value which is defined as a percentage of the corresponding clock cycle time. Defines an absolute delay constraint value. The units attribute can be used to specify units if needed. The default units are ns. Defines a constraint indicating how an input is to be driven. The preferred methodology is to specify a library cell in technology independent fashion. The implemention tool should assume that the associated signal is driven by the specified cell, or that the drive strength of the input signal is indicated by the specified resistance value. Specifes a drive resistance for the input signal. Defines a constraint indicating the type of load on an output signal. Indicates how many loads of the specified cell are connected. If not present, 3 is assumed. Indicates an explicit load capacitance on an output signal. Defines one or more logical paths within a component. Defines a valid path starting point. This can be a clock, an input port, a sequential cell, or a clock or data out pin of a sequential cell. These do not have to be objects that are directly represented in the SPIRIT data model. Use the pathElement attribute to indicate the type of object referred to it if might be ambiguous. Defines a valid path ending point. This can be a clock, an output port, a sequential cell, or a clock or data in pin of a sequential cell. These do not have to be objects that are directly represented in the SPIRIT data model. Use the pathElement attribute to indicate the type of object referred to if it might be ambiguous. Defines a valid path ending point. This can be a clock, an output port, a sequential cell, or a clock or data in pin of a sequential cell. These do not have to be objects that are directly represented in the SPIRIT data model. Use the pathElement attribute to indicate the type of object referred to if it might be ambiguous. Defines a set of pins, ports, cells, or nets through which the desired path(s) must pass. These do not have to be objects that are directly represented in the SPIRIT data model. Use the pathElement attribute to indicate the type of object referred to if it might be ambiguous. Defines a set of pins, ports, cells, or nets through which the desired path(s) must pass. These do not have to be objects that are directly represented in the SPIRIT data model. Use the pathElement attribute to indicate the type of object referred to if it might be ambiguous. Defines a false path timing exception. Defines a multi-cycle path timing exception. Defines a point-to-point timing exception. The pathEdge attribute can be used to restrict the constraint to rising or falling edges, and the delayType attribute can be used to restrict the constraint to imply a minimum path constraint or a maximum path constraint. Defines signal and/or component constraints associated with circuit design rules. Minimum capacitance value for this component or signal. The units attribute can be used to indicate the units associated with the capacitance value. Default unit value is 'pf'. Maximum capacitance value for this component or signal. Minimum transition delay for this component or signal. Minimum transition delay for a rising edge transition for this component or signal. Minimum transition delay for a falling edge transition for this component or signal. Maximum transition delay for this component or signal. Maximum transition delay for a rising edge transition for this component or signal. Maximum transition delay for a falling edge transition for this component or signal. Maximum fanout value for this component or signal. Defines the set of implementation constraints associated with a component. If multiple componentConstraints elements are used, each must have a unique value for the constraintSet attribute. List of componentConstraints elements for this component. Defines constraints that apply to a component signal. If multiple signalConstraints elements are used, each must have a unique value for the constraintSet attribute. The optional element vector specify the bits of a vector for which the constraints apply. The vaules of left and right must be within the range of the port. If the vector is not specified then the constraints apply to all the bits of the port. The optional elements left and right can be used to select a bit-slice of a vector. The optional elements left and right can be used to select a bit-slice of a vector. List of signalConstraints elements for a component signal. Defines constraints that apply to a signal in a bus definition. If multiple busDefSignalConstraints are used, each must have a unique value of the constraintSet attribute. These constraints are carried over to the associated component signal as default values. Grouping of constraints related to point to point timing requirements. A reference to a set of constraints (signalConstraints, componentConstraints, or busDefConstraints).