Component view type Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from spirit:fileType. The tool values are defined by the SPIRIT Consortium, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. References a SPIRIT design or configuration document (by VLNV) that provides a design for the component The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. A value of 'true' indicates that this value must match the language being generated for the design. Language specific name to identity the model. Verilog or SystemVerilog this is the module name. For VHDL this is, with ()’s, the entity(architecture) name pair or without, a single configuration name. For SystemC this is the class name. Default command and flags used to build derived files from the sourceName files in the referenced file sets. Container for white box element references. Reference to a white box element which is visible within this view. Abstraction view type Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from spirit:fileType. The tool values are defined by the SPIRIT Consortium, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. A value of 'true' indicates that this value must match the language being generated for the design. Language specific name to identity the model. Verilog or SystemVerilog this is the module name. For VHDL this is, with ()’s, the entity(architecture) name pair or without a single configuration name. For SystemC this is the class name. Default command and flags used to build derived files from the sourceName files in the referenced file sets. Model information. View container Single view of a component Port container Model parameter name value pairs container A model parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used. Model information for an abstractor. View container Single view of an abstractor Port container Model parameter name value pairs container A model parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicate how the model parameter is to be used. Model information. Reference to a whiteboxElement within a view. The 'name' attribute must refer to a whiteboxElement defined within this component. The whiteboxPath elements (as a set) define the name(s) needed to define the entire white box element in this view. The view specific name for a portion of the white box element. Optional bound on the path name. If not specified, the size of the element referred to by pathName must be determined from the referenced element. Indicates the left bound value for the associated path name. Indicates the right bound values for the associated path name. Reference to a whiteboxElement defined within this component.