Technology name. Defines the type of implementation (ASIC or FPGA). The standard cell area (in mm2 or logic cells) out of synthesis, without taking into account any extra space. The area (in mm2 or logic cells) of the other cells (macro, memories) that are part of the component. If not provided, it is assumed to be zero, i.e. the component is assumed to be made of logic cells only. The width in mm of the biggest macro that may constraint the component floorplan. The height in mm of the biggest macro that may constraint the component floorplan. The estimated area (in mm2 or logic cells) of the component after physical implementation. The difference between totalArea and the sum of (gateArea + macroArea) typically represents provision for routing, congestion and floorplan constraints as estimated by the provider. The number of sequential elements (i.e. leaf cells) seen by each clock port. This value may be dependent on one or more parameters to account for configurable IPs. A list of combinational paths crossing the component by means of output ports (sink) directly dependent on input ports (sources). Enumerated file types known by Standard PDP Extension.