
Please find below examples of use of 1685-2009-SE standard extensions wrt/ PDP
(Physical Design Planning) for FPGA and ASIC.

Those examples are based on the existing LEON2 audioSubSystem already present
within IP-XACT 1685-2009 examples & tutorial, but originally without those new 
standard extensions.

1/ FPGA

  Examples based on existing design (spiritconsortium.org Leon2RTL audioSubSystem 5.0) and its components

  - components with accellera-pdp:areaEstimation info wrt/ xilinx virtex-7 technology (from FPGA synthesis results)
     - ahbbus25alda.xml
     - ahbliteram.xml
     - ahbrom.xml
     - ahbstatSlave.xml
     - apbbus2pp.xml
     - apbmst.xml
     - dma.xml
     - mp3Decode.xml
  - top component with xilinx XDC fileset
     - audioSubSystem.xdc
     - audioSubSystem.xml 


2/ ASIC

  Examples based on existing design (spiritconsortium.org Leon2RTL audioSubSystem 2.0) and its components

  - components with accellera-pdp:areaEstimation info wrt/ cmos032lp technology (from RTL synthesis result)
    + accellera-pdp:registerCount on clock ports (extracted from RTL) 
    + accellera-pdp:combinationalPaths information (extracted from RTL)
    - ahbbus25.xml
    - ahbram.xml
    - ahbrom.xml
    - apbbus1.xml
    - apbmst.xml
    - dma.xml
    - mp3Decode.xml
  - original design (unchanged)
    - audioSubSystem.xml 
    - design_audioSubSystem.xml
  - TGI generator written in PERL to collect gateArea from a design
    - get_area.pl
  - Result of this TGI generator on the audioSubSystem
    - area.rpt



