Constant Index
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B |
| BEGIN_REQ
| BEGIN_RESP
E |
| END_REQ
| END_RESP
U |
| UNINITIALIZED_PHASE
| UVM_ACTIVE
| UVM_ALL_DROPPED
| UVM_BACKDOOR
| UVM_BIG_ENDIAN
| UVM_BIG_FIFO
| UVM_BIN
| UVM_BODY
| UVM_CALL_HOOK
| UVM_CHECK
| UVM_COUNT
| UVM_CREATED
| UVM_CVR_ADDR_MAP
| UVM_CVR_ALL
| UVM_CVR_FIELD_VALS
| UVM_CVR_REG_BITS
| UVM_DEC
| UVM_DEEP
| UVM_DEFAULT_PATH
| UVM_DISPLAY
| UVM_DO_ALL_REG_MEM_TESTS
| UVM_DO_MEM_ACCESS
| UVM_DO_MEM_WALK
| UVM_DO_REG_ACCESS
| UVM_DO_REG_BIT_BASH
| UVM_DO_REG_HW_RESET
| UVM_DO_SHARED_ACCESS
| UVM_DROPPED
| UVM_ENDED
| UVM_ENUM
| UVM_EQ
| UVM_ERROR
| UVM_EXIT
| UVM_EXPORT
| UVM_FATAL
| UVM_FIELD
| UVM_FINISHED
| UVM_FRONTDOOR
| UVM_FULL
| UVM_GT
| UVM_GTE
| UVM_HAS_X
| UVM_HEX
| UVM_HIER
| UVM_HIGH
| UVM_IMPLEMENTATION
| UVM_INFO
| UVM_IS_OK
| UVM_LITTLE_ENDIAN
| UVM_LITTLE_FIFO
| UVM_LOG
| UVM_LOW
| UVM_LT
| UVM_LTE
| UVM_MEDIUM
| UVM_MEM
| UVM_NE
| UVM_NO_ACTION
| UVM_NO_CHECK
| UVM_NO_COVERAGE
| UVM_NO_ENDIAN
| UVM_NO_HIER
| UVM_NONE
| UVM_NOT_OK
| UVM_OCT
| UVM_PASSIVE
| UVM_PHASE_CLEANUP
| UVM_PHASE_DOMAIN
| UVM_PHASE_DONE
| UVM_PHASE_DORMANT
| UVM_PHASE_ENDED
| UVM_PHASE_EXECUTING
| UVM_PHASE_IMP
| UVM_PHASE_JUMPING
| UVM_PHASE_NODE
| UVM_PHASE_READY_TO_END
| UVM_PHASE_SCHEDULE
| UVM_PHASE_SCHEDULED
| UVM_PHASE_STARTED
| UVM_PHASE_SYNCING
| UVM_PHASE_TERMINAL
| UVM_PHASE_UNINITIALIZED
| UVM_PORT
| UVM_POST_BODY
| UVM_POST_START
| UVM_PRE_BODY
| UVM_PRE_START
| UVM_PREDICT
| UVM_PREDICT_DIRECT
| UVM_PREDICT_READ
| UVM_PREDICT_WRITE
| UVM_RAISED
| UVM_READ
| UVM_REAL
| UVM_REAL_DEC
| UVM_REAL_EXP
| UVM_REFERENCE
| UVM_REG
| UVM_RM_RECORD
| UVM_SEQ_ARB_FIFO
| UVM_SEQ_ARB_RANDOM
| UVM_SEQ_ARB_STRICT_FIFO
| UVM_SEQ_ARB_STRICT_RANDOM
| UVM_SEQ_ARB_USER
| UVM_SEQ_ARB_WEIGHTED
| UVM_SEQ_LIB_ITEM
| UVM_SEQ_LIB_RAND
| UVM_SEQ_LIB_RANDC
| UVM_SEQ_LIB_USER
| UVM_SHALLOW
| UVM_STOP
| UVM_STOPPED
| UVM_STRING
| UVM_TIME
| UVM_TLM_ACCEPTED
| UVM_TLM_ADDRESS_ERROR_RESPONSE
| UVM_TLM_BURST_ERROR_RESPONSE
| UVM_TLM_BYTE_ENABLE_ERROR_RESPONSE
| UVM_TLM_COMMAND_ERROR_RESPONSE
| UVM_TLM_COMPLETED
| UVM_TLM_GENERIC_ERROR_RESPONSE
| UVM_TLM_IGNORE_COMMAND
| UVM_TLM_INCOMPLETE_RESPONSE
| UVM_TLM_OK_RESPONSE
| UVM_TLM_READ_COMMAND
| UVM_TLM_UPDATED
| UVM_TLM_WRITE_COMMAND
| UVM_UNFORMAT2
| UVM_UNFORMAT4
| UVM_UNSIGNED
| UVM_WARNING
| UVM_WRITE

Beginning of request phase
Beginning of response phase
End of request phase
End of response phase
Defaults for constructor
“Active” mode
all objections have been dropped
Use the back door
Most-significant bytes first in consecutive addresses
Most-significant bytes first at the same address
Selects binary (%b) format
The sequence is started and the uvm_sequence_base::body() task is being executed.
Callback the report hook methods
Read and check
Counts the number of reports with the COUNT attribute.
The sequence has been allocated.
Individual register and memory addresses
All coverage models
Field values
Individual register bits
Selects decimal (%d) format
Objects are deep copied (object must implement uvm_object::copy method)
Operation specified by the context
Sends the report to the standard output
Run all of the above
Run uvm_mem_access_seq
Run uvm_mem_walk_seq
Run uvm_reg_access_seq
Run uvm_reg_bit_bash_seq
Run uvm_reg_hw_reset_seq
Run uvm_reg_mem_shared_access_seq
an objection was raised
The sequence has completed the execution of the uvm_sequence_base::body() task.
Selects enumeration value (name) format
equal
Indicates a real problem.
Terminates the simulation immediately.
The port provides the interface that is its type parameter via a connection to some other export or implementation.
Indicates a problem from which simulation cannot recover.
Field
The sequence is completely finished executing.
Use the front door
Report is issued if configured verbosity is set to UVM_FULL or above.
greater than
greater than or equal to
Operation completed successfully bit had unknown bits.
Selects hexadecimal (%h) format
Provide info based on the hierarchical context
Report is issued if configured verbosity is set to UVM_HIGH or above.
The port provides the interface that is its type parameter, and it is bound to the component that implements the interface.
Informative message.
Operation completed successfully
Least-significant bytes first in consecutive addresses
Least-significant bytes first at the same address
Sends the report to the file(s) for this (severity,id) pair
Report is issued if configured verbosity is set to UVM_LOW or above.
less than
less than or equal to
Report is issued if configured verbosity is set to UVM_MEDIUM or above.
Memory location
not equal
No action is taken
Read only
None
Byte ordering not applicable
Provide info from the local context
Report is always printed.
Operation completed with error
Selects octal (%o) format
“Passive” mode
all processes related to phase are being killed
This object represents an entire graph segment that executes in parallel with the ‘run’ phase.
A phase is done after it terminated execution.
The schedule is not currently operating on the phase node, however it will be scheduled at some point in the future.
phase completed execution, now running phase_ended() callback
An executing phase is one where the phase callbacks are being executed.
The phase object is used to traverse the component hierarchy and call the component phase method as well as the phase_started and phase_ended callbacks.
all processes related to phase are being killed and all predecessors are forced into the DONE state.
The object represents a simple node instance in the graph.
no objections remain in this phase or in any predecessors of its successors or in any sync’d phases.
The object represents a portion of the phasing graph, typically consisting of several NODE types, in series, parallel, or both.
At least one immediate predecessor has completed.
phase ready to execute, running phase_started() callback
All predecessors complete, checking that all synced phases (e.g.
This internal object serves as the termination NODE for a SCHEDULE phase object.
The state is uninitialized.
The port requires the interface that is its type parameter.
The sequence is started and the uvm_sequence_base::post_body() task is being executed.
The sequence is started and the uvm_sequence_base::post_start() task is being executed.
The sequence is started and the uvm_sequence_base::pre_body() task is being executed.
The sequence is started and the uvm_sequence_base::pre_start() task is being executed.
Operation derived from observations by a bus monitor via the uvm_reg_predictor class.
Predicted value is as-is
Predict based on the specified value having been read
Predict based on the specified value having been written
an objection was raised
Read operation
Selects real (%g) in exponential or decimal format, whichever format results in the shorter printed output
Selects real (%f) in decimal format
Selects real (%e) in exponential format
Only object handles are copied.
Register
Sends the report to the recorder
Requests are granted in FIFO order (default)
Requests are granted randomly
Requests at highest priority granted in fifo order
Requests at highest priority granted in randomly
Arbitration is delegated to the user-defined function, user_priority_arbitration.
Requests are granted randomly by weight
Emit only items, no sequence execution
Random sequence selection
Random cyclic sequence selection
Apply a user-defined random-selection algorithm
Objects are shallow copied using default SV copy.
Causes $stop to be executed, putting the simulation into interactive mode.
The sequence has been forcibly ended by issuing a uvm_sequence_base::kill() on the sequence.
Selects string (%s) format
Selects time (%t) format
Transaction has been accepted
Invalid address specified
Invalid burst specified
Invalid byte enabling specified
Invalid command specified
Execution of transaction is complete
Bus operation had an error
No bus operation.
Transaction was not delivered to target
Bus operation completed successfully
Bus read operation
Transaction has been modified
Bus write operation
Selects unformatted 2 value data (%u) format
Selects unformatted 4 value data (%z) format
Selects unsigned decimal (%u) format
Indicates a potential problem.
Write operation