# Register Sequence Classes

This section defines the base classes used for register stimulus generation.

Contents

Register Sequence Classes | This section defines the base classes used for register stimulus generation.
uvm_reg_sequence | This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
uvm_reg_frontdoor | Facade class for register and memory frontdoor access.

## uvm_reg_sequence

This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.

- When used as a base for user-defined RegModel test sequences, this class provides convenience methods for reading and writing registers and memories. Users implement the body() method to interact directly with the RegModel model (held in the model property) or indirectly via the delegation methods in this class.
- When used as a translation sequence, objects of this class are executed directly on a bus sequencer which are used in support of a layered sequencer use model, a pre-defined convert-and-execute algorithm is provided.

Register operations do not require extending this class if none of the above services are needed. Register test sequences can be extend from the base uvm_sequence #(REQ,RSP) base class or even from outside a sequence.

Note- The convenience API not yet implemented.

Summary

uvm_reg_sequence
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
Class Hierarchy
BASE
uvm_reg_sequence
Class Declaration
> class uvm_reg_sequence #(
> | type | BASE | = | uvm_sequence #(uvm_reg_item)
> ) extends BASE
BASE | Specifies the sequence type to extend from.
model | Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.
adapter | Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
reg_seqr | Layered upstream “register” sequencer.
new | Create a new instance, giving it the optional name.
body | Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.
do_reg_item | Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e.
Convenience Write/ Read API | The following methods delegate to the corresponding method in the register or memory element.
write_reg | Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument.
read_reg | Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.
poke_reg | Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument.
peek_reg | Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument.
update_reg | Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument.
mirror_reg | Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument.
write_mem | Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument.
read_mem | Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument.
poke_mem | Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument.
peek_mem | Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument.

### BASE

Specifies the sequence type to extend from.

When used as a translation sequence running on a bus sequencer, BASE must be compatible with the sequence type expected by the bus sequencer.

When used as a test sequence running on a particular sequencer, BASE must be compatible with the sequence type expected by that sequencer.

When used as a virtual test sequence without a sequencer, BASE does not need to be specified, i.e. the default specialization is adequate.

To maximize opportunities for reuse, user-defined RegModel sequences should “promote” the BASE parameter.

>     class my_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item))
>                                   extends uvm_reg_sequence #(BASE);

This way, the RegModel sequence can be extended from user-defined base sequences.

### model

> uvm_reg_block model

Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

### adapter

> uvm_reg_adapter adapter

Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

### reg_seqr

> uvm_sequencer #(
> | uvm_reg_item
> ) reg_seqr

Layered upstream “register” sequencer.

Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to “pull” from an upstream sequencer.

### new

> function new (
> | string | name | = | "uvm_reg_sequence_inst"
> )

Create a new instance, giving it the optional name.

### body

> virtual task body()

Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.

User-defined RegModel test sequences must override body() and not call super.body(), else a warning will be issued and the calling process not return.

### do_reg_item

> virtual task do_reg_item(
> | uvm_reg_item | rw
> )

Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e. m_sequencer). Uses the configured adapter to convert the register transaction into the type expected by this sequencer.

### Convenience Write/ Read API

The following methods delegate to the corresponding method in the register or memory element. They allow a sequence body() to do reads and writes without having to explicitly supply itself to parent sequence argument. Thus, a register write

>     model.regA.write(status, value, .parent(this));

can be written instead as

>     write_reg(model.regA, status, value);

### write_reg

> virtual task write_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument. Thus,

>     write_reg(model.regA, status, value);

is equivalent to

>     model.regA.write(status, value, .parent(this));

### read_reg

> virtual task read_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument. Thus,

>     read_reg(model.regA, status, value);

is equivalent to

>     model.regA.read(status, value, .parent(this));

### poke_reg

> virtual task poke_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument. Thus,

>     poke_reg(model.regA, status, value);

is equivalent to

>     model.regA.poke(status, value, .parent(this));

### peek_reg

> virtual task peek_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument. Thus,

>     peek_reg(model.regA, status, value);

is equivalent to

>     model.regA.peek(status, value, .parent(this));

### update_reg

> virtual task update_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument. Thus,

>     update_reg(model.regA, status, value);

is equivalent to

>     model.regA.update(status, value, .parent(this));

### mirror_reg

> virtual task mirror_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_check_e | check | = | UVM_NO_CHECK,
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument. Thus,

>     mirror_reg(model.regA, status, UVM_CHECK);

is equivalent to

>     model.regA.mirror(status, UVM_CHECK, .parent(this));

### write_mem

> virtual task write_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument. Thus,

>     write_mem(model.regA, status, offset, value);

is equivalent to

>     model.regA.write(status, offset, value, .parent(this));

### read_mem

> virtual task read_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument. Thus,

>     read_mem(model.regA, status, offset, value);

is equivalent to

>     model.regA.read(status, offset, value, .parent(this));

### poke_mem

> virtual task poke_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument. Thus,

>     poke_mem(model.regA, status, offset, value);

is equivalent to

>     model.regA.poke(status, offset, value, .parent(this));

### peek_mem

> virtual task peek_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument. Thus,

>     peek_mem(model.regA, status, offset, value);

is equivalent to

>     model.regA.peek(status, offset, value, .parent(this));

## uvm_reg_frontdoor

Facade class for register and memory frontdoor access.

User-defined frontdoor access sequence

Base class for user-defined access to register and memory reads and writes through a physical interface.

By default, different registers and memories are mapped to different addresses in the address space and are accessed via those exclusively through physical addresses.

The frontdoor allows access using a non-linear and/or non-mapped mechanism. Users can extend this class to provide the physical access to these registers.

Summary

uvm_reg_frontdoor
Facade class for register and memory frontdoor access.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_sequence_item))
uvm_reg_frontdoor
Class Declaration
> virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_sequence_item)
> )
Variables |
rw_info | Holds information about the register being read or written
sequencer | Sequencer executing the operation
Methods |
new | Constructor, new object given optional name.

### Variables

### rw_info

> uvm_reg_item rw_info

Holds information about the register being read or written

### sequencer

> uvm_sequencer_base sequencer

Sequencer executing the operation

### Methods

### new

> function new(
> | string | name | = | ""
> )

Constructor, new object given optional name.

> class uvm_reg_sequence #(
> | type | BASE | = | uvm_sequence #(uvm_reg_item)
> ) extends BASE

This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.

> virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_sequence_item)
> )

Facade class for register and memory frontdoor access.

> uvm_reg_block model

Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

> uvm_reg_adapter adapter

Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

> uvm_sequencer #(
> | uvm_reg_item
> ) reg_seqr

Layered upstream “register” sequencer.

> function new (
> | string | name | = | "uvm_reg_sequence_inst"
> )

Create a new instance, giving it the optional name.

> virtual task body()

Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.

> virtual task do_reg_item(
> | uvm_reg_item | rw
> )

Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e.

> virtual task write_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument.

> virtual task write(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Write the specified value in this register

> virtual task read_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.

> virtual task read(
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Read the current value from this register

> virtual task poke_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument.

> virtual task poke(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_sequence_base | parent | = | null,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Deposit the specified value in this register

> virtual task peek_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument.

> virtual task peek(
> | output | uvm_status_e | status, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_sequence_base | parent | = | null,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Read the current value from this register

> virtual task update_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument.

> virtual task update(
> | output | uvm_status_e | status, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Updates the content of the register in the design to match the desired value

> virtual task mirror_reg(
> | input | uvm_reg | rg, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_check_e | check | = | UVM_NO_CHECK,
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument.

> virtual task mirror(
> | output | uvm_status_e | status, |  |
> | input | uvm_check_e | check | = | UVM_NO_CHECK,
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Read the register and update/check its mirror value

> virtual task write_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument.

> virtual task write(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Write the specified value in a memory location

> virtual task read_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument.

> virtual task read(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | uvm_path_e | path | = | UVM_DEFAULT_PATH,
> | input | uvm_reg_map | map | = | null,
> | input | uvm_sequence_base | parent | = | null,
> | input | int | prior | = | -1,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Read the current value from a memory location

> virtual task poke_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument.

> virtual task poke(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | input | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_sequence_base | parent | = | null,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Deposit the specified value in a memory location

> virtual task peek_mem(
> | input | uvm_mem | mem, |  |
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument.

> virtual task peek(
> | output | uvm_status_e | status, |  |
> | input | uvm_reg_addr_t | offset, |  |
> | output | uvm_reg_data_t | value, |  |
> | input | string | kind | = | "",
> | input | uvm_sequence_base | parent | = | null,
> | input | uvm_object | extension | = | null,
> | input | string | fname | = | "",
> | input | int | lineno | = | 0
> )

Read the current value from a memory location

> virtual class uvm_sequence #(
> | type | REQ | = | uvm_sequence_item,
> | type | RSP | = | REQ
> ) extends uvm_sequence_base

The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.

> uvm_reg_item rw_info

Holds information about the register being read or written

> uvm_sequencer_base sequencer

Sequencer executing the operation

> function new(
> | string | name | = | ""
> )

Constructor, new object given optional name.