# Shared Register and Memory Access Test Sequences

This section defines sequences for testing registers and memories that are shared between two or more physical interfaces, i.e. are associated with more than one uvm_reg_map instance.

Contents

Shared Register and Memory Access Test Sequences | This section defines sequences for testing registers and memories that are shared between two or more physical interfaces, i.e.
uvm_reg_shared_access_seq | Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.
uvm_mem_shared_access_seq | Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.
uvm_reg_mem_shared_access_seq | Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.

## uvm_reg_shared_access_seq

Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.

If bit-type resource named “NO_REG_TESTS” or “NO_REG_SHARED_ACCESS_TEST” in the “REG::” namespace matches the full name of the register, the register is not tested.

>     uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
>                                "NO_REG_TESTS", 1, this);

Registers that contain fields with unknown access policies cannot be tested.

The DUT should be idle and not modify any register during this test.

Summary

uvm_reg_shared_access_seq
Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_shared_access_seq
Class Declaration
> class uvm_reg_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )
Variables |
rg | The register to be tested

### Variables

### rg

> uvm_reg rg

The register to be tested

## uvm_mem_shared_access_seq

Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.

If bit-type resource named “NO_REG_TESTS”, “NO_MEM_TESTS”, “NO_REG_SHARED_ACCESS_TEST” or “NO_MEM_SHARED_ACCESS_TEST” in the “REG::” namespace matches the full name of the memory, the memory is not tested.

>     uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
>                                "NO_MEM_TESTS", 1, this);

The DUT should be idle and not modify the memory during this test.

Summary

uvm_mem_shared_access_seq
Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_mem_shared_access_seq
Class Declaration
> class uvm_mem_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )
Variables |
mem | The memory to be tested

### Variables

### mem

> uvm_mem mem

The memory to be tested

## uvm_reg_mem_shared_access_seq

Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.

If bit-type resource named “NO_REG_TESTS”, “NO_MEM_TESTS”, “NO_REG_SHARED_ACCESS_TEST” or “NO_MEM_SHARED_ACCESS_TEST” in the “REG::” namespace matches the full name of the block, the block is not tested.

>     uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
>                                "NO_REG_TESTS", 1, this);

Summary

uvm_reg_mem_shared_access_seq
Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_mem_shared_access_seq
Class Declaration
> class uvm_reg_mem_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )
Variables |
model | The block to be tested
reg_seq | The sequence used to test one register
mem_seq | The sequence used to test one memory
Methods |
body | Executes the Shared Register and Memory sequence
do_block | Test all of the registers and memories in a block
reset_blk | Reset the DUT that corresponds to the specified block abstraction class.

### Variables

### model

The block to be tested

>     uvm_reg_block model;

### reg_seq

> protected uvm_reg_shared_access_seq reg_seq

The sequence used to test one register

### mem_seq

> protected uvm_mem_shared_access_seq mem_seq

The sequence used to test one memory

### Methods

### body

> virtual task body()

Executes the Shared Register and Memory sequence

### do_block

> protected virtual task do_block(
> | uvm_reg_block | blk
> )

Test all of the registers and memories in a block

### reset_blk

> virtual task reset_blk(
> | uvm_reg_block | blk
> )

Reset the DUT that corresponds to the specified block abstraction class.

Currently empty. Will rollback the environment’s phase to the reset phase once the new phasing is available.

In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.

> class uvm_reg_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.

> class uvm_mem_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.

> class uvm_reg_mem_shared_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.

> class uvm_reg_map extends uvm_object

> uvm_reg rg

The register to be tested

> uvm_mem mem

The memory to be tested

> protected uvm_reg_shared_access_seq reg_seq

The sequence used to test one register

> protected uvm_mem_shared_access_seq mem_seq

The sequence used to test one memory

> virtual task body()

Executes the Shared Register and Memory sequence

> protected virtual task do_block(
> | uvm_reg_block | blk
> )

Test all of the registers and memories in a block

> virtual task reset_blk(
> | uvm_reg_block | blk
> )

Reset the DUT that corresponds to the specified block abstraction class.