# Port Base Classes

Contents

Port Base Classes |
uvm_port_component_base | This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.
uvm_port_component #(PORT) | See description of uvm_port_component_base for information about this class
uvm_port_base #(IF) | Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.

## uvm_port_component_base

This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase. The sub-class, uvm_port_component #(PORT), implements this interface.

The connectivity lists are returned in the form of handles to objects of this type. This allowing traversal of any port’s fan-out and fan-in network through recursive calls to get_connected_to and get_provided_to. Each port’s full name and type name can be retrieved using get_full_name and get_type_name methods inherited from uvm_component.

Summary

uvm_port_component_base
This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.
Class Hierarchy
uvm_void
uvm_object
uvm_report_object
uvm_component
uvm_port_component_base
Class Declaration
> virtual class uvm_port_component_base extends uvm_component
Methods |
get_connected_to | For a port or export type, this function fills list with all of the ports, exports and implementations that this port is connected to.
get_provided_to | For an implementation or export type, this function fills list with all of the ports, exports and implementations that this port is provides its implementation to.
is_port |
is_export |
is_imp | These function determine the type of port.

### Methods

### get_connected_to

> pure virtual function void get_connected_to(
> | ref | uvm_port_list | list
> )

For a port or export type, this function fills list with all of the ports, exports and implementations that this port is connected to.

### get_provided_to

> pure virtual function void get_provided_to(
> | ref | uvm_port_list | list
> )

For an implementation or export type, this function fills list with all of the ports, exports and implementations that this port is provides its implementation to.

### is_port

> pure virtual function bit is_port()

### is_export

> pure virtual function bit is_export()

### is_imp

> pure virtual function bit is_imp()

These function determine the type of port. The functions are mutually exclusive; one will return 1 and the other two will return 0.

## uvm_port_component #(PORT)

See description of uvm_port_component_base for information about this class

Summary

uvm_port_component #(PORT)
See description of uvm_port_component_base for information about this class
Class Hierarchy
uvm_void
uvm_object
uvm_report_object
uvm_component
uvm_port_component_base
uvm_port_component#(PORT)
Class Declaration
> class uvm_port_component #(
> | type | PORT | = | uvm_object
> ) extends uvm_port_component_base
Methods |
get_port | Retrieve the actual port object that this proxy refers to.

### Methods

### get_port

> function PORT get_port()

Retrieve the actual port object that this proxy refers to.

## uvm_port_base #(IF)

Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.

The uvm_port_base extends IF, which is the type of the interface implemented by derived port, export, or implementation. IF is also a type parameter to uvm_port_base.

IF | The interface type implemented by the subtype to this base port

The UVM provides a complete set of ports, exports, and imps for the OSCI- standard TLM interfaces. They can be found in the ../src/tlm/ directory. For the TLM interfaces, the IF parameter is always uvm_tlm_if_base #(T1,T2).

Just before uvm_component::end_of_elaboration_phase, an internal uvm_component::resolve_bindings process occurs, after which each port and export holds a list of all imps connected to it via hierarchical connections to other ports and exports. In effect, we are collapsing the port’s fanout, which can span several levels up and down the component hierarchy, into a single array held local to the port. Once the list is determined, the port’s min and max connection settings can be checked and enforced.

uvm_port_base possesses the properties of components in that they have a hierarchical instance path and parent. Because SystemVerilog does not support multiple inheritance, uvm_port_base cannot extend both the interface it implements and uvm_component. Thus, uvm_port_base contains a local instance of uvm_component, to which it delegates such commands as get_name, get_full_name, and get_parent.

Summary

uvm_port_base #(IF)
Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.
Class Hierarchy
IF
uvm_port_base#(IF)
Class Declaration
> virtual class uvm_port_base #(
> | type | IF | = | uvm_void
> ) extends IF
Methods |
new | The first two arguments are the normal uvm_component constructor arguments.
get_name | Returns the leaf name of this port.
get_full_name | Returns the full hierarchical name of this port.
get_parent | Returns the handle to this port’s parent, or null if it has no parent.
get_comp | Returns a handle to the internal proxy component representing this port.
get_type_name | Returns the type name to this port.
min_size | Returns the minimum number of implementation ports that must be connected to this port by the end_of_elaboration phase.
max_size | Returns the maximum number of implementation ports that must be connected to this port by the end_of_elaboration phase.
is_unbounded | Returns 1 if this port has no maximum on the number of implementation ports this port can connect to.
is_port |
is_export |
is_imp | Returns 1 if this port is of the type given by the method name, 0 otherwise.
size | Gets the number of implementation ports connected to this port.
set_default_index | Sets the default implementation port to use when calling an interface method.
connect | Connects this port to the given provider port.
debug_connected_to | The debug_connected_to method outputs a visual text display of the port/export/imp network to which this port connects (i.e., the port’s fanout).
debug_provided_to | The debug_provided_to method outputs a visual display of the port/export network that ultimately connect to this port (i.e., the port’s fanin).
resolve_bindings | This callback is called just before entering the end_of_elaboration phase.
get_if | Returns the implementation (imp) port at the given index from the array of imps this port is connected to.

### Methods

### new

> function new (
> | string | name, |  |
> | uvm_component | parent, |  |
> | uvm_port_type_e | port_type, |  |
> | int | min_size | = | 0,
> | int | max_size | = | 1
> )

The first two arguments are the normal uvm_component constructor arguments.

The port_type can be one of UVM_PORT, UVM_EXPORT, or UVM_IMPLEMENTATION.

The min_size and max_size specify the minimum and maximum number of implementation (imp) ports that must be connected to this port base by the end of elaboration. Setting max_size to UVM_UNBOUNDED_CONNECTIONS sets no maximum, i.e., an unlimited number of connections are allowed.

By default, the parent/child relationship of any port being connected to this port is not checked. This can be overridden by configuring the port’s check_connection_relationships bit via uvm_config_int::set(). See connect for more information.

### get_name

> function string get_name()

Returns the leaf name of this port.

### get_full_name

> virtual function string get_full_name()

Returns the full hierarchical name of this port.

### get_parent

> virtual function uvm_component get_parent()

Returns the handle to this port’s parent, or null if it has no parent.

### get_comp

> virtual function uvm_port_component_base get_comp()

Returns a handle to the internal proxy component representing this port.

Ports are considered components. However, they do not inherit uvm_component. Instead, they contain an instance of uvm_port_component #(PORT) that serves as a proxy to this port.

### get_type_name

> virtual function string get_type_name()

Returns the type name to this port. Derived port classes must implement this method to return the concrete type. Otherwise, only a generic “uvm_port”, “uvm_export” or “uvm_implementation” is returned.

### min_size

Returns the minimum number of implementation ports that must be connected to this port by the end_of_elaboration phase.

### max_size

Returns the maximum number of implementation ports that must be connected to this port by the end_of_elaboration phase.

### is_unbounded

> function bit is_unbounded ()

Returns 1 if this port has no maximum on the number of implementation ports this port can connect to. A port is unbounded when the max_size argument in the constructor is specified as UVM_UNBOUNDED_CONNECTIONS.

### is_port

> function bit is_port ()

### is_export

> function bit is_export ()

### is_imp

> function bit is_imp ()

Returns 1 if this port is of the type given by the method name, 0 otherwise.

### size

> function int size ()

Gets the number of implementation ports connected to this port. The value is not valid before the end_of_elaboration phase, as port connections have not yet been resolved.

### set_default_index

> function void set_default_index (
> | int | index
> )

Sets the default implementation port to use when calling an interface method. This method should only be called on UVM_EXPORT types. The value must not be set before the end_of_elaboration phase, when port connections have not yet been resolved.

### connect

> virtual function void connect (
> | this_type | provider
> )

Connects this port to the given provider port. The ports must be compatible in the following ways

- Their type parameters must match
- The provider’s interface type (blocking, non-blocking, analysis, etc.) must be compatible. Each port has an interface mask that encodes the interface(s) it supports. If the bitwise AND of these masks is equal to the this port’s mask, the requirement is met and the ports are compatible. For example, a uvm_blocking_put_port #(T) is compatible with a uvm_put_export #(T) and uvm_blocking_put_imp #(T) because the export and imp provide the interface required by the uvm_blocking_put_port.
- Ports of type UVM_EXPORT can only connect to other exports or imps.
- Ports of type UVM_IMPLEMENTATION cannot be connected, as they are bound to the component that implements the interface at time of construction.

In addition to type-compatibility checks, the relationship between this port and the provider port will also be checked if the port’s check_connection_relationships configuration has been set. (See new for more information.)

#### Relationships, when enabled, are checked are as follows

- If this port is a UVM_PORT type, the provider can be a parent port, or a sibling export or implementation port.
- If this port is a UVM_EXPORT type, the provider can be a child export or implementation port.

If any relationship check is violated, a warning is issued.

Note- the uvm_component::connect_phase method is related to but not the same as this method. The component’s connect method is a phase callback where port’s connect method calls are made.

### debug_connected_to

> function void debug_connected_to (
> | int | level | = | 0,
> | int | max_level | = | -1
> )

The debug_connected_to method outputs a visual text display of the port/export/imp network to which this port connects (i.e., the port’s fanout).

This method must not be called before the end_of_elaboration phase, as port connections are not resolved until then.

### debug_provided_to

> function void debug_provided_to (
> | int | level | = | 0,
> | int | max_level | = | -1
> )

The debug_provided_to method outputs a visual display of the port/export network that ultimately connect to this port (i.e., the port’s fanin).

This method must not be called before the end_of_elaboration phase, as port connections are not resolved until then.

### resolve_bindings

> virtual function void resolve_bindings()

This callback is called just before entering the end_of_elaboration phase. It recurses through each port’s fanout to determine all the imp destinations. It then checks against the required min and max connections. After resolution, size returns a valid value and get_if can be used to access a particular imp.

This method is automatically called just before the start of the end_of_elaboration phase. Users should not need to call it directly.

### get_if

> function uvm_port_base #(
> | IF
> ) get_if(int index=0)

Returns the implementation (imp) port at the given index from the array of imps this port is connected to. Use size to get the valid range for index. This method can only be called at the end_of_elaboration phase or after, as port connections are not resolved before then.

> virtual class uvm_port_component_base extends uvm_component

This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.

> class uvm_port_component #(
> | type | PORT | = | uvm_object
> ) extends uvm_port_component_base

See description of uvm_port_component_base for information about this class

> virtual class uvm_port_base #(
> | type | IF | = | uvm_void
> ) extends IF

Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.

> virtual class uvm_void

The uvm_void class is the base class for all UVM classes.

> virtual class uvm_object extends uvm_void

The uvm_object class is the base class for all UVM data and hierarchical classes.

> class uvm_report_object extends uvm_object

The uvm_report_object provides an interface to the UVM reporting facility.

> virtual class uvm_component extends uvm_report_object

The uvm_component class is the root base class for UVM components.

> pure virtual function void get_connected_to(
> | ref | uvm_port_list | list
> )

For a port or export type, this function fills list with all of the ports, exports and implementations that this port is connected to.

> pure virtual function void get_provided_to(
> | ref | uvm_port_list | list
> )

For an implementation or export type, this function fills list with all of the ports, exports and implementations that this port is provides its implementation to.

> pure virtual function bit is_port()

> pure virtual function bit is_export()

> pure virtual function bit is_imp()

These function determine the type of port.

> function PORT get_port()

Retrieve the actual port object that this proxy refers to.

> function new (
> | string | name, |  |
> | uvm_component | parent, |  |
> | uvm_port_type_e | port_type, |  |
> | int | min_size | = | 0,
> | int | max_size | = | 1
> )

The first two arguments are the normal uvm_component constructor arguments.

> function string get_name()

Returns the leaf name of this port.

> virtual function string get_full_name()

Returns the full hierarchical name of this port.

> virtual function uvm_component get_parent()

Returns the handle to this port’s parent, or null if it has no parent.

> virtual function uvm_port_component_base get_comp()

Returns a handle to the internal proxy component representing this port.

> virtual function string get_type_name()

Returns the type name to this port.

> function bit is_unbounded ()

Returns 1 if this port has no maximum on the number of implementation ports this port can connect to.

> function bit is_port ()

> function bit is_export ()

> function bit is_imp ()

Returns 1 if this port is of the type given by the method name, 0 otherwise.

> function int size ()

Gets the number of implementation ports connected to this port.

> function void set_default_index (
> | int | index
> )

Sets the default implementation port to use when calling an interface method.

> virtual function void connect (
> | this_type | provider
> )

Connects this port to the given provider port.

> function void debug_connected_to (
> | int | level | = | 0,
> | int | max_level | = | -1
> )

The debug_connected_to method outputs a visual text display of the port/export/imp network to which this port connects (i.e., the port’s fanout).

> function void debug_provided_to (
> | int | level | = | 0,
> | int | max_level | = | -1
> )

The debug_provided_to method outputs a visual display of the port/export network that ultimately connect to this port (i.e., the port’s fanin).

> virtual function void resolve_bindings()

This callback is called just before entering the end_of_elaboration phase.

> function uvm_port_base #(
> | IF
> ) get_if(int index=0)

Returns the implementation (imp) port at the given index from the array of imps this port is connected to.

> virtual class uvm_tlm_if_base #(
> | type | T1 | = | int,
> | type | T2 | = | int
> )

This class declares all of the methods of the TLM API.

> virtual function void end_of_elaboration_phase(
> | uvm_phase | phase
> )

The uvm_end_of_elaboration_phase phase implementation method.

> virtual function void resolve_bindings ()

Processes all port, export, and imp connections.
The port requires the interface that is its type parameter.
The port provides the interface that is its type parameter via a connection to some other export or implementation.
The port provides the interface that is its type parameter, and it is bound to the component that implements the interface.

> virtual function void connect_phase(
> | uvm_phase | phase
> )

The uvm_connect_phase phase implementation method.