# Register Defines

Summary

Register Defines
Macros |
`UVM_REG_ADDR_WIDTH | Maximum address width in bits
`UVM_REG_DATA_WIDTH | Maximum data width in bits
`UVM_REG_BYTENABLE_WIDTH | Maximum number of byte enable bits
`UVM_REG_CVR_WIDTH | Maximum number of bits in a uvm_reg_cvr_t coverage model set.

### Macros

### `UVM_REG_ADDR_WIDTH

Maximum address width in bits

Default value is 64. Used to define the uvm_reg_addr_t type.

### `UVM_REG_DATA_WIDTH

Maximum data width in bits

Default value is 64. Used to define the uvm_reg_data_t type.

### `UVM_REG_BYTENABLE_WIDTH

Maximum number of byte enable bits

Default value is one per byte in `UVM_REG_DATA_WIDTH. Used to define the uvm_reg_byte_en_t type.

### `UVM_REG_CVR_WIDTH

Maximum number of bits in a uvm_reg_cvr_t coverage model set.

Default value is 32.

Coverage model value set with `UVM_REG_CVR_WIDTH bits.
2-state address value with `UVM_REG_ADDR_WIDTH bits
2-state data value with `UVM_REG_DATA_WIDTH bits
Maximum data width in bits
2-state byte_enable value with `UVM_REG_BYTENABLE_WIDTH bits