# Register Access Test Sequences

This section defines sequences that test DUT register access via the available frontdoor and backdoor paths defined in the provided register model.

Contents

Register Access Test Sequences | This section defines sequences that test DUT register access via the available frontdoor and backdoor paths defined in the provided register model.
uvm_reg_single_access_seq | Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.
uvm_reg_access_seq | Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.
uvm_reg_mem_access_seq | Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.

## uvm_reg_single_access_seq

Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.

If bit-type resource named “NO_REG_TESTS” or “NO_REG_ACCESS_TEST” in the “REG::” namespace matches the full name of the register, the register is not tested.

>     uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
>                                "NO_REG_TESTS", 1, this);

Registers without an available backdoor or that contain read-only fields only, or fields with unknown access policies cannot be tested.

The DUT should be idle and not modify any register during this test.

Summary

uvm_reg_single_access_seq
Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_single_access_seq
Class Declaration
> class uvm_reg_single_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )
Variables |
rg | The register to be tested

### Variables

### rg

> uvm_reg rg

The register to be tested

## uvm_reg_access_seq

Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.

If bit-type resource named “NO_REG_TESTS” or “NO_REG_ACCESS_TEST” in the “REG::” namespace matches the full name of the block, the block is not tested.

>     uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
>                                "NO_REG_TESTS", 1, this);

Summary

uvm_reg_access_seq
Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_access_seq
Class Declaration
> class uvm_reg_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )
Variables |
model | The block to be tested.
reg_seq | The sequence used to test one register
Methods |
body | Executes the Register Access sequence.
do_block | Test all of the registers in a block
reset_blk | Reset the DUT that corresponds to the specified block abstraction class.

### Variables

### model

The block to be tested. Declared in the base class.

>     uvm_reg_block model;

### reg_seq

> protected uvm_reg_single_access_seq reg_seq

The sequence used to test one register

### Methods

### body

> virtual task body()

Executes the Register Access sequence. Do not call directly. Use seq.start() instead.

### do_block

> protected virtual task do_block(
> | uvm_reg_block | blk
> )

Test all of the registers in a block

### reset_blk

> virtual task reset_blk(
> | uvm_reg_block | blk
> )

Reset the DUT that corresponds to the specified block abstraction class.

Currently empty. Will rollback the environment’s phase to the reset phase once the new phasing is available.

In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.

## uvm_reg_mem_access_seq

Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.

Blocks and registers with the NO_REG_TESTS or the NO_REG_ACCESS_TEST attribute are not verified.

Summary

uvm_reg_mem_access_seq
Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_mem_access_seq
Class Declaration
> class uvm_reg_mem_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

> class uvm_reg_single_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.

> class uvm_reg_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.

> class uvm_reg_mem_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.

> class uvm_mem_access_seq extends uvm_reg_sequence #(
> | uvm_sequence | #(uvm_reg_item)
> )

Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.

> uvm_reg rg

The register to be tested

> protected uvm_reg_single_access_seq reg_seq

The sequence used to test one register

> virtual task body()

Executes the Register Access sequence.

> protected virtual task do_block(
> | uvm_reg_block | blk
> )

Test all of the registers in a block

> virtual task reset_blk(
> | uvm_reg_block | blk
> )

Reset the DUT that corresponds to the specified block abstraction class.